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gl830 usb 2.0 to sata bridge controller datasheet revision 1.02 aug. 21, 2007 genesys logic, inc.
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 2 copyright: copyright ? 2007 genesys logic incorporated. all rights reserv ed. no part of the materials may be reproduced in any form or by any means without prio r written consent of genesys logic, inc. disclaimer: all materials are provided "as is" without express or implied warranty of any kind. no license or right is granted under any pat ent or trademark of genesys logic inc.. genesys logic hereby disclaims all warranties and conditions in regard to materials, including all wa rranties, implied or express, of merchantability, fitness for any partic ular purpose, and non-infringement of intellectual property. in no e vent shall genesys logic be liable for any damages including, without limita tion, damages resulting from loss of information or profits. please be adv ised that the materials may contain errors or ommisions. genesys logic may make changes to the materials or to the products described therein at a ny time without notice. trademarks: is a registrated trademark of genesys logic, inc. all trademarks are the properties of their respect ive owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beishin rd., shindian city, taipei, taiwan tel: (886-2) 8913-1888 fax: (886-2) 6629-6168 http://www.genesyslogic.com
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 3 revision history revision date description 1.00 06/14/2007 first formal release 1.01 7/17/2007 add 48 and 128pin description 1.02 08/21/2007 modify lqfp48/64/128 description
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 4 table of contents chapter 1 general description..................... .............................. 8 chapter 2 features ................................ .............................................. 9 chapter 3 pin assignment .......................... .................................... 10 3.1 p inouts ................................................... ................................................. 10 3.2 p in l ist ................................................... ................................................. 13 3.3 p in d escriptions ................................................... ................................ 15 chapter 4 block diagram........................... ................................... 22 chapter 5 function description .................... ........................... 23 5.1 utm................................................ ................................................... ...... 23 5.2 sie................................................ ................................................... ......... 23 5.3 ep0/ep3 fifo and b ulk b uffer ................................................... ..... 23 5.4 o peration r egister ................................................... .......................... 23 5.5 spi i nterface ................................................... ..................................... 23 5.6 phy l ayer ................................................... .......................................... 23 5.7 l ink l ayer ................................................... .......................................... 23 5.8 t ransport l ayer ................................................... ............................... 23 5.9 a pplication l ayer ................................................... ............................ 23 chapter 6 electrical characteristics.............. ................. 24 6.1 a bsolute m aximum r atings ................................................... ........... 24 6.2 t emperature c onditions ................................................... ................ 24 6.3 dc c haracteristics ................................................... ......................... 24 6.3.1 i/o type digital pins ........................ ............................................... 24 6.3.2 usb interface dc characteristics ............. ................................... 25 6.3.3 sata interface dc characteristics ............ ................................. 25 6.3.4 reference clock input requirement ............ ................................ 25 6.3.5 reference resistor requirement ............... .................................... 25 6.4 ac c haracteristics ................................................... ......................... 25 6.4.1 usb interface ac characteristics ............. ................................... 25 6.4.2 sata interface ac characteristics ............ ................................. 25
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 5 chapter 7 package dimension....................... .............................. 26 chapter 8 ordering information .................... ........................ 29
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 6 list of figures f igure 3.1 - 48 p in lqfp p inout d iagram ................................................... ............... 10 f igure 3.2 - 64 p in lqfp p inout d iagram ................................................... ............... 11 f igure 3.3 - 128 p in lqfp p inout d iagram ................................................... ............ 12 f igure 4.1 - b lock d iagram ................................................... ...................................... 22 f igure 7.1 ? gl830 48 p in lqfp p ackage ................................................... ............... 26 f igure 7.2 - gl830 64 p in lqfp p ackage ................................................... ................ 27 f igure 7.3 - gl830 128 p in lqfp p ackage ................................................... .............. 28
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 7 list of tables t able 3.1 ? 48 p in l ist ................................................... ................................................. 13 t able 3.2 ? 64 p in l ist ................................................... ................................................. 13 t able 3.3 ? 128 p in l ist ................................................... ............................................... 14 t able 3.4 ? 48 p in d escriptions ................................................... ................................. 15 t able 3.5 ? 64 p in d escriptions ................................................... ................................. 16 t able 3.6 ? 128 p in d escriptions ................................................... ............................... 18 t able 6.1 - m aximum r atings ................................................... ................................... 24 t able 6.2 - t emperature c onditions ................................................... ...................... 24 t able 6.3 - i/o t ype digital pins ................................................... ............................... 24 t able 6.6 - r eference c lock i nput r equirement .................................................. 2 5 t able 6.7 - r eference r esistor r equirement ................................................... ...... 25 t able 8.1 - o rdering i nformation ................................................... .......................... 29
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 8 chapter 1 general description the gl830 is a highly-compatible, low cost usb 2.0 to sata bridge controller, which integrates genesys logic own design high speed utmi (usb 2.0 transceiv er macrocell interface) transceiver/receiver and se rial ata phy. as a one-chip solution which complies with universal serial bus specification rev. 2.0 and se rial ata specification rev. 2.6. there are totally 4 end points in the gl830 controller, control (0), bulk i n (1), bulk out (2), and interrupt (3). by complies with the us b storage class specification ver.1.0 (bulk only pr otocol), the gl830 can support not only plug and play but al so windows vista/ xp/ 2000/ me default driver. the gl830 uses 25mhz crystal and slew-rate controlled p ads to reduce the emi issue. with 64-pin lqfp (7mmx7mm) package, the gl830 is the best cost/ perf ormance solution to fit different situations in the usb 2.0 high speed storage class applications such as sata hdd and odd.
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 9 chapter 2 features complies with universal serial bus specification rev. 2.0. complies with usb storage class specification ver .1.0. (bulk only protocol) operating system supported: win vista/ win xp / 2 000 / me / 98 / 98se; mac os 9.x / x. integrated usb 2.0 transceiver macrocell interfac e (utmi) transceiver and serial interface engine (s ie). support 4 endpoints: control (0) / bulk read (1) / bulk write (2) / interrupt (3). 64 / 512 bytes data payload for full / high speed bulk endpoint. complies with serial ata specification rev. 2.6. support sata hot-plug support spread spectrum clocking to reduce emi support partial/slumber power management provide adjustable tx signal amplitude and pre-em phasis level provide specified oob signal detection and transm ission embedded turbo 8051. rom size: 12k words; ram size: 1280 bytes. (bulk buffer: 512 words, mc ram: 256 bytes) supports power down mode and usb suspend indicato r. supports usb 2.0 test mode features. supports 4 pio and 4gpio for programmable ap. supports device power control for power on/off wh en running suspend mode. provides led indicator for full speed and high sp eed . using 25 mhz external clock to provide better emi . 3.3v power input; 5v tolerance pad. supports wakeup ability. embedded regulator (3.3v to 1.8v). embedded regulator (5v to 3.3v). provides spi interface for finger print (only for 64 pin package). available in 48/64/128-pin lqfp.
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 10 chapter 3 pin assignment 3.1 pinouts lqfp - 48 gnd 1 gpio0 2 gpio3 3 pio3 4 hrst_ 5 cvdd 6 vdd 7 gnd 8 test 9 pio0 10 pio1 11 cvdd 12 gnd cvdd x1 x2 vdd gnd vdd cvdd agnd avdd dp dm 36 35 34 33 32 31 30 29 28 27 26 25 rterm 37 pllvdd 38 pllvss 39 txvss 40 txvdd 41 txp 42 txn 43 rxn 44 rxp 45 rxvdd 46 rxvss 47 cvdd 48 agnd rref avdd nc gpio1 nc pio2 gpio2 nc v5 vdd gnd 24 23 22 21 20 19 18 17 16 15 14 13 figure 3.1 - 48 pin lqfp pinout diagram
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 11 gl830 lqfp - 64 txp 57 txn 58 rxn 59 rxp 60 rxvdd 61 rxvss 62 cvdd 63 gnd 64 pllvdd 49 pllvss 50 rxpext 51 rxnext 52 txnext 53 txpext 54 txvss 55 txvdd 56 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 6 gpio2 nc v5 vdd gnd cvdd nc nc nc nc nc gpio1 nc nc pio2 nc 7 8 9 10 11 12 13 14 15 16 5 4 3 2 1 43 42 41 40 39 38 37 36 35 34 33 44 45 46 47 48 figure 3.2 - 64 pin lqfp pinout diagram
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 12 gl830 lqfp - 128 pio0 33 pio1 34 rom_a0 35 dd2 36 rom_d0 37 dd13 38 rom_d7 39 dd1 40 rom_d1 41 dd14 42 rom_d6 43 dd0 44 rom_d2 45 dd15 46 cvdd 47 gnd 48 mode1 49 vdd 50 vdd 51 v5 52 rom_d5 53 dmarq 54 gpio2 55 diow_ 56 pio2 57 dior_ 58 t_rom 59 iordy 60 gpio1 61 dmack_ 62 nc 97 nc 98 nc 99 nc 100 nc 101 nc 102 nc 103 pllvdd 104 pllvdd 105 pllvss 106 rxpext 107 rxnext 108 txnext 109 txpext 110 txvss 111 txvdd 112 txp 113 txn 114 rxn 115 rxp 116 rxvdd 117 rxvss 118 cvdd 119 gnd 120 nc 121 rom_a8 122 rom_a7 123 rom_a9 124 rom_a6 125 rom_a10 126 areset_ 127 spdsel 128 phyrdy 63 gpio4 64 figure 3.3 - 128 pin lqfp pinout diagram
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 13 3.2 pin list table 3.1 ? 48 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 gnd p 13 gnd p 25 dm b 37 rterm a 2 gpio0 b 14 vdd p 26 dp b 38 pllvdd p 3 gpio3 b 15 v5 p 27 avdd p 39 pllvss p 4 pio3 b 16 nc - 28 agnd p 40 txvss p 5 hrst_ i 17 gpio2 b 29 cvdd p 41 txvdd p 6 cvdd p 18 pio2 b 30 vdd p 42 txp o 7 vdd p 19 nc - 31 gnd p 43 txn o 8 gnd p 20 gpio1 b 32 vdd p 44 rxn i 9 test i 21 nc - 33 x2 b 45 rxp i 10 pio0 b 22 avdd p 34 x1 i 46 rxvdd p 11 pio1 b 23 rref a 35 cvdd p 47 rxvss p 12 cvdd p 24 agnd p 36 gnd p 48 cvdd p table 3.2 ? 64 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 gpio0 b 17 nc - 33 avdd p 49 pllvdd p 2 gpio3 b 18 nc - 34 rref a 50 pllvss p 3 pio3 b 19 nc - 35 agnd p 51 rxpext i 4 nc - 20 cvdd p 36 dm b 52 rxnext i 5 hrst_ i 21 gnd p 37 dp b 53 txnext o 6 nc - 22 vdd p 38 avdd3 p 54 txpext o 7 nc - 23 v5 p 39 agnd3 p 55 txvss p 8 cvdd p 24 nc - 40 cvdd p 56 txvdd p 9 vdd p 25 gpio2 b 41 vdd p 57 txp o 10 mode i 26 nc - 42 gnd p 58 txn o 11 gnd p 27 pio2 b 43 vdd p 59 rxn i 12 test i 28 nc - 44 x2 b 60 rxp i 13 nc - 29 nc - 45 x1 i 61 rxvdd p
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 14 14 nc - 30 gpio1 b 46 cvdd p 62 rxvss p 15 pio0 b 31 nc - 47 gnd p 63 cvdd p 16 pio1 b 32 nc - 48 rterm a 64 gnd p table 3.3 ? 128 pin list pin# pin name type pin# pin name type pin# pin name type pin# pin name type 1 gpio0 b 33 pio0 b 65 aintrq b 97 nc - 2 gpio3 b 34 pio1 b 66 avdd p 98 nc - 3 pio4 b 35 rom_a0 o 67 avdd p 99 nc - 4 pio3 b 36 dd2 b 68 rref a 100 nc - 5 rom_a5 o 37 rom_d0 b 69 agnd p 101 nc - 6 dd7 b 38 dd13 b 70 agnd p 102 nc - 7 rom_a11 o 39 rom_d7 b 71 dm b 103 nc - 8 dd8 b 40 dd1 b 72 dp b 104 pllvdd p 9 hrst_ i 41 rom_d1 b 73 avdd p 105 pllvdd p 10 dd6 b 42 dd14 b 74 agnd p 106 pllvss p 11 rom_a4 o 43 rom_d6 b 75 gnd p 107 rxpext i 12 dd9 b 44 dd0 b 76 gnd p 108 rxnext i 13 rom_a12 o 45 rom_d2 b 77 cvdd p 109 txnext o 14 dd5 b 46 dd15 b 78 da1 b 110 txpext o 15 rom_a3 o 47 cvdd p 79 da0 b 111 txvss p 16 cvdd p 48 gnd p 80 nc - 112 txvdd p 17 cvdd p 49 mode1 i 81 da2 b 113 txp o 18 vdd p 50 vdd p 82 rom_d3 b 114 txn o 19 mod0 i 51 vdd p 83 cs0_ b 115 rxn i 20 gnd p 52 v5 i 84 rom_d4 b 116 rxp i 21 dd10 b 53 rom_d5 b 85 cs1_ b 117 rxvdd p 22 rom_a13 o 54 dmarq b 86 gnd p 118 rxvss p 23 test i 55 gpio2 b 87 vdd p 119 cvdd p 24 txd o 56 diow_ b 88 vdd p 120 gnd p 25 rxd b 57 pio2 b 89 gnd p 121 nc -
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 15 26 dd4 b 58 dior_ b 90 gnd p 122 rom_a8 o 27 rom_a2 o 59 t_rom i 91 vdd p 123 rom_a7 o 28 dd11 b 60 iordy b 92 x2 b 124 rom_a9 o 29 rom_a14 o 61 gpio1 b 93 x1 i 125 rom_a6 o 30 dd3 b 62 dmack_ b 94 vdd p 126 rom_a10 o 31 rom_a1 o 63 phyrdy o 95 gnd p 127 areset_ b 32 dd12 b 64 gpio4 b 96 rterm a 128 spdsel i 3.3 pin descriptions table 3.4 ? 48 pin descriptions usb interface pin name pin# type description rref 23 a reference resistor dm 25 b hs d- dp 26 b hs d+ avdd 22,27 p usb analog 3.3v power agnd 24,28 p usb analog ground sata interface pin name pin# type description rterm 37 a reference resistor pllvdd 38 p 1.8v power supplies for internal pll pllvss 39 p ground for internal pll txvss 40 p ground for transceiver part txvdd 41 p 1.8v power supplies for transceiver part txp 42 o sata differential transmit tx+ txn 43 o sata differential transmit tx- rxn 44 i sata differential receive rx- rxp 45 i sata differential receive rx+ rxvdd 46 p 1.8v power supplies for receiver part rxvss 47 p ground for receiver part digital power and ground pin name pin# type description
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 16 cvdd 6,12,29, 35,48 p 1.8v digital power vdd 7,14 30, 32 p 3.3v digital power gnd 1,8,13, 31,36 p digital ground v5 15 p 5v power input miscellaneous interface pin name pin# type description test 9 i (pd) test mode input x2 33 b crystal output x1 34 i crystal input hrst_ 5 i (pu) reset pin gpio0~3 2,20,17,3 b (pu) general purpose i/o #0~#3 pio0~3 10,11,18, 4 b (pd) programmable i/o #0~#3 nc 16,19,21 - no connection table 3.5 ? 64 pin descriptions usb interface pin name pin# type description rref 34 a reference resistor dm 36 b hs d- dp 37 b hs d+ avdd 33,38 p usb analog 3.3v power agnd 35,39 p usb analog ground sata interface pin name pin# type description rterm 48 a reference resistor pllvdd 49 p 1.8v power supplies for internal pll pllvss 50 p ground for internal pll rxpext 51 i esata differential receive rx+ rxnext 52 i esata differential receive rx-
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 17 txnext 53 o esata differential transmit tx- txpext 54 o esata differential transmit tx+ txvss 55 p ground for transceiver part txvdd 56 p 1.8v power supplies for transceiver part txp 57 o sata differential transmit tx+ txn 58 o sata differential transmit tx- rxn 59 i sata differential receive rx- rxp 60 i sata differential receive rx+ rxvdd 61 p 1.8v power supplies for receiver part rxvss 62 p ground for receiver part digital power and ground pin name pin# type description cvdd 8,20,40, 46,63 p 1.8v digital power vdd 9,22,41, 43 p 3.3v digital power gnd 11,21,42, 47,64 p digital ground v5 23 p 5v power input miscellaneous interface pin name pin# type description test 12 i (pd) test mode input x2 44 b crystal output x1 45 i crystal input hrst_ 5 i (pu) reset pin mode 10 i (pd) mode select (0=> usb to sata; 1=> esata to sata) gpio0~3 1,30,25,2 b (pu) general purpose i/o #0~#3 pio0~3 15,16,27, 3 b (pd) programmable i/o #0~#3 nc 4,6,7,13, 14,17,18, 19,24,26, 28,29,31, 32 - no connection
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 18 table 3.6 ? 128 pin descriptions usb interface pin name pin# type description rref 68 a reference resistor dm 71 b hs d- dp 72 b hs d+ avdd 66,67,73 p usb analog 3.3v power agnd 69,70,74 p usb analog ground sata interface pin name pin# type description rterm 96 a reference resistor pllvdd 104,105 p 1.8v power supplies for internal pll pllvss 106 p ground for internal pll rxpext 107 i esata differential receive rx+ rxnext 108 i esata differential receive rx- txnext 109 o esata differential transmit tx- txpext 110 o esata differential transmit tx+ txvss 111 p ground for transceiver part txvdd 112 p 1.8v power supplies for transceiver part txp 113 o sata differential transmit tx+ txn 114 o sata differential transmit tx- rxn 115 i sata differential receive rx- rxp 116 i sata differential receive rx+ rxvdd 117 p 1.8v power supplies for receiver part rxvss 118 p ground for receiver part digital power and ground pin name pin# type description cvdd 16,17,47, 77,119 p 1.8v digital power vdd 18,50,51 87,88,91, 94 p 3.3v digital power gnd 20,48,75, 76,86,89, 90,95, 120 p digital ground
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 19 v5 52 p 5v power input ata/ atapi interface (host mode) pin name pin# type description dd0~15 44,40,36, 30,26,14, 10,6,8,12, 21,28,32, 38,42,46 b ide data bus areset_ 127 i (pu) device reset cs1_, cs0_ 85, 83 i (pu) chip select #1,#0 da0~2 79,78,81 i (pd) ide address #2,#1,#0 intrq 65 o ide interrupt input dmack_ 62 i (pu) ide acknowledge iordy 60 o ide ready dior_ 58 i (pu) ide read signal diow_ 56 i (pu) ide write signal dmarq 54 o ide request ata/ atapi interface (device mode) pin name pin# type description dd0~15 44,40,36, 30,26,14, 10,6,8,12, 21,28,32, 38,42,46 b ide data bus areset_ 127 o device reset cs1_, cs0_ 85, 83 o chip select #1,#0 da0~2 79,78,81 o ide address #2,#1,#0 intrq 65 i (pd) ide interrupt input dmack_ 62 o ide acknowledge iordy 60 i (pu) ide ready dior_ 58 o ide read signal diow_ 56 o ide write signal dmarq 54 i (pd) ide request
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 20 miscellaneous interface pin name pin# type description test 23 i (pd) test mode input x2 92 b crystal output x1 93 i crystal input hrst_ 9 i (pu) reset pin mode0,1 19,49 i (pd) mode select 00=> usb to sata; 10=> esata to sata; 01=> usb to pata; 11=> sata to pata when mode0,1=11, pio1=0 is device mode. when mode0,1=11, pio1=1 is host mode. gpio0~4 1,61,55,2, 64 b (pu) general purpose i/o #0~#4 pio0~4 33,34,57, 4,3 b (pd) programmable i/o #0~#4 txd 24 o (pu) 8051 uart txd rxd 25 b (pu) 8051 uart rxd spdsel 128 i (pd) 0 => force in 1.5g; 1 => negotiate interface speed with attached device (1.5g or 3g) phyrdy 63 o sata phy ready t_rom 59 i (pd) 0 => internal rom; 1 => external rom rom_a0~14 35,31,27, 15,11,5, 125,123, 122,124, 126,7,13, 22,29 o rom address #0~#14 rom_d0~7 37,41,45, 82,84,53, 43,39 b (pd) rom data #0~#7 nc 80,97,98, 99,100, 101,102, 103 - no connection notation: type o output i input b bi-directional b/i bi-directional, default input b/o bi-directional, default output p power / ground a analog
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 21 so automatic output low when suspend pu internal pull up pd internal pull down odpu open drain with internal pull up
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 22 chapter 4 block diagram 8051 core rom ram gpio spi operation register usb transport layer link layer phy layer utm sie bulk buffer ep0/3 fifo controller application layer sata esata pata figure 4.1 - block diagram
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 23 chapter 5 function description 5.1 utm the usb 2.0 transceiver macrocell, it?s the analog circuitry that handles the low level usb protocol a nd signaling, and shifts the clock domain of the data from the usb 2.0 rate to one that is compatible wit h the general logic. 5.2 sie the serial interface engine, which contains the usb pid and address recognition logic, and other seque ncing and state machine logic to handle usb packets and t ransactions. 5.3 ep0/ep3 fifo and bulk buffer endpoint 0/3 fifo: the control and interrupt fifo. it is composed of tx03fifo and rx03fifo, with 64-byte fifo each, and it is used for endpoint 0/3 data transfer. bulk buffer: it is constructed in interleaved archi tecture and composed by two data buffers which is u sed to store data transferred between usb host and ide device. 5.4 operation register it is a register space to store status information and to control the functions of gl830 by 8051. 5.5 spi interface the serial peripheral interface is a serial, synchr onous communication protocol. it is compatible with motorola?s spi specifications. 5.6 phy layer it has elastic buffer and supports receiver detecti on, data serialization and de-serialization. 5.7 link layer the link layer transmits and receives frames, trans mits primitives based on control signals from the t ransport layer, and receives primitives from the phy layer w hich are converted to control signals to the transp ort layer. 5.8 transport layer the transport layer constructs frame information st ructures for transmission and decomposes received f rame information structure 5.9 application layer the application layer translates the ata operation onto internal protocols.
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 24 chapter 6 electrical characteristics 6.1 absolute maximum ratings table 6.1 - maximum ratings symbol parameter min. typ. max. unit v io digital i/o pad power supply voltage 3.0 3.3 3.6 v vcore digital power supply voltage 1.62 1.8 1.98 v v ausb analog power supply voltage for usb phy 3.0 3.3 3 .6 v v asata analog power supply voltage for sata phy 1.62 1.8 1.98 v v esd static discharge voltage 4000 v t a ambient temperature 0 100 o c 6.2 temperature conditions table 6.2 - temperature conditions item value storage temperature -50 o c ~ 150 o c operating temperature 0 o c ~ 70 o c 6.3 dc characteristics 6.3.1 i/o type digital pins table 6.3 - i/o type digital pins parameter min. typ. max. unit current sink @ v ol = 0.4v 10.58 14.21 16.87 ma current output @ v oh = 2.4v (ttl high) 14.74 27.46 43.0 ma falling slew rate at 30 pf loading capacitance 0.5 6 0.91 1.28 v/ns rising slew rate at 30 pf loading capacitance 0.5 8 0.91 1.72 v/ns schmitt trigger low to high threshold point 1.4 1.5 1.6 v schmitt trigger low to high threshold point 1.4 1.5 1.6 v pad internal pull up resister 37.87k 64.7k 108.11k ohms pad internal pull down resister 29.85k 59.45k 134.26k ohms
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 25 6.3.2 usb interface dc characteristics the gl830 conforms to dc characteristics for univer sal serial bus specification rev. 2.0. please refer to this specification for more information. 6.3.3 sata interface dc characteristics the gl830 conforms to dc characteristics for serial ata specification rev. 2.6. please refer to this specification for more information. 6.3.4 reference clock input requirement table 6.6 - reference clock input requirement parameter min. typ. max. unit x1 crystal frequency 25 mhz x1 cycle time 40 ns 6.3.5 reference resistor requirement table 6.7 - reference resistor requirement parameter min. typ. max. unit usb reference resistor 680 ohms sata reference resistor 5.1k ohms 6.4 ac characteristics 6.4.1 usb interface ac characteristics the gl830 conforms to all timing diagrams and speci fications for universal serial bus specification re v. 2.0. please refer to this specification for more informa tion. 6.4.2 sata interface ac characteristics the gl830 conforms to all timing diagrams and speci fications for serial ata specification rev. 2.6. pl ease refer to this specification for more information.
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 26 chapter 7 package dimension figure 7.1 ? gl830 48 pin lqfp package
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 27 figure 7.2 - gl830 64 pin lqfp package
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 28 l 1 control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d e d1 e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 16.00 basic 16.00 basic 14.00 basic 14.00 basic 0.630 basic 0.630 basic 0.551 basic 0.551 basic 0.05 1.35 1.40 1.60 0.15 1.45 00 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 00 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.07 0.008 0.008 0.003 0.003 0.40 basic 12.40 basic 12.40 basic 0.016 basic 0.488 basic 0.488 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.13 0.60 0.16 0.20 0.75 0.23 0.004 0.018 0.008 0.005 0.024 0.006 0.008 0.030 0.009 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. seating plane c c ccc 0 1 - 0 - a a2 a1 c e 0 . 0 5 d1 d2 b d a b b a d d c h aaa bbb ddd 4x 4x m c b a s s d s e e 1 e 2 a b d 1 128 32 33 64 65 96 97 gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h gl830 aaaaaaagaa ywwxxxxxxxx date code lot code internal no. code no. green package figure 7.3 - gl830 128 pin lqfp package
gl830 usb2.0 to sata bridge controller ?2007 genesys logic inc. - all rights reserved. page 29 chapter 8 ordering information table 8.1 - ordering information part number package green version status gl830-mngxx 48-pin lqfp green package xx available GL830-MSGXX 64-pin lqfp green package xx available gl830-mxgxx 128-pin lqfp green package xx available

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